processor level
英 [ˈprəʊsesə(r) ˈlevl]
美 [ˈprɑːsesər ˈlevl]
网络 处理器层; 处理层; 处理器级别
双语例句
- As the name implies, this governor's goal is to get the maximum performance out of a system by setting the processor clock speed to the maximum level and leaving it there.
顾名思义，此调控器的目标的通过将处理器时钟速度设置为最大级别而实现最大的系统性能。 - As you can see from the above mentioned list, deploying a web service using a JSR-181 processor could significantly reduce the level of effort for developing and deploying a Java based web service.
从上面提到的列表中可以看出，使用JSR-181处理器部署Web服务可以大幅度减少基于Java的Web服务的开发和部署的工作量。 - The values that showed any significant difference were the individual request response times and the processor busy level on the Lotus Domino servers.
在LotusDomino服务器中，显示有意义的单个请求响应时间和处理器繁忙级别的区别。 - A physical processor is organized as different execution units at the hardware level, for example, fixed point and floating point operation units.
在硬件级别中，物理处理器是作为不同的执行单元进行组织的，例如定点和浮点操作单元。 - It is essential not to confuse the frequency of a processor with its performance level.
重要的是不要混淆频率的处理器，其性能水平。 - The verification method, used in a media DSP processor named Spock ( developed by Zhejiang University and C-sky Microsystems Co., Ltd), increase design automation level and save the verification time.
本验证方案成功应用于在浙江大学和中天微系统有限公司合作开发的拥有自主知识产权的媒体DSP处理器Spock的设计中，提高了验证自动化及标准化水平，缩短了设计过程中验证的时间。 - Recommend the compiler design and implementation methods which use in embedded processor and compiles high-level language.
介绍了一种用于嵌入式处理器Si02的高级语言编译器的设计与实现方法。 - The most important aim of this method is to model a retargetable processor model at the early stage of the system level design, so as to get optimum results for specific applications.
该设计基于可配置处理器核，在设计早期阶段对SoC系统快速建模，以获得针对具体应用算法的最优性能。 - However, to ensure the safety of data, efficiency will be lost during the processor of protecting data, which is not anticipated by the application of telecom level.
而要保证数据的安全性，在进行数据保护时就会损失效率，这也是电信级应用所不想看到的结果。 - With the guidance of low level signal detection theory, this subject has developed a low level signal detection platform based on high speed DSP processor, which can realize the reliable detection of the μ-volt level even lower level array induction signal.
本课题以微弱信号检测理论方法为指导，研制基于高速DSP处理器的微弱信号检测平台，可实现μ伏级甚至幅值更低的阵列感应微弱信号的可靠检测。 - The combination of DSP processors and reconfigurable computing technology has the promising potential to improve the single DSP processor performance to a higher level.
而可重构技术和DSP处理器的结合也使得单DSP处理器性能有望得到很大提升。 - A new load index was particularly defined for the case to make sure a processor's load level.
定义了一种新的复合型负载指标来衡量各处理机的负载程度。 - This paper provides a method which makes the monolithic processor be able to correct dislocation and work normally and reliably in case the voltage falls below the originally set level.
提出了一种方法&过冲法，可以在某些不满足复位电压（必须大于最低工作电压）的情况下，使得单片机能够正常可靠地复位和工作。 - A new kind of intelligent control with single chip processor in swilling toilet seat is designed to improve the capabilities of the product and make the control to water level, water temperature and washing time intelligently.
采用单片机进行智能控制，实现喷淋座垫智能化，克服了以往人工调整水杆和人工限时的弊病，提高了产品的性能和实用价值。 - On the another hand, along with the development of microprocessor and embedded application, there are many kind of high performance embedded processor supporting the MMU and high level protection mode.
另一方面，随着微处理器技术和嵌入式应用的发展，出现了各种各样的高性能的嵌入式微处理器，并且普遍支持MMU和高级保护模式。 - With the improvement in the performance of digital signal processor ( DSP) and field programmable gate array ( FPGA), more and more functions are implemented in the lower level of the control system.
随着数字信号处理器（DSP）、现场可编程逻辑门阵列（FPGA）性能的不断提高，运动控制系统的控制功能正在不断分散到控制系统的底层。 - In this paper, an embedded 16-bit processor core is designed, based on the characteristics of the wireless communication algorithm and instruction level acceleration technology.
文章结合无线通信处理算法的特点，利用指令级加速技术，设计了一种基于无线通信中复数运算的16位嵌入式处理器核。 - A complete study on branch prediction mechanisms uncovers the optimal scheme for embedded processor after tradeoff among area, power and performance. This work belongs to typical low-power research at microarchitecture level.
针对嵌入式处理器结构，从功耗和性能两方面研究了转移预测机制，并提出了嵌入式处理器转移预测器的优选方案，也为考虑功耗因素后的嵌入式处理器结构设计提供了研究范例； - Design and Implementation of VLIW Processor System Level Verification Platform
VLIW处理器系统级验证平台的设计与实现 - This paper first analyzes the trading mechanism of multiple mode trade and introduces the concept of hybrid virtual multiple processor. It presents a software modal for multi-mode trade engine based on message dispatching and two level request queues in the computing environment containing hybrid virtual multiple processors.
通过分析多模式交易的交易机制，引入虚拟混杂多处理机的概念，提出了虚拟混杂多处理机计算环境中基于消息分拣和双级请求队列的多模式交易引擎的软件结构模型。 - The driving power of market asks for VT-x, a processor level support for virtual machine of Intel.
市场的驱动催生了VT-x，Intel在芯片级为对虚拟机提供支持的一种技术。 - Digital welding power source adopt digital signal processor ( TMS320F2812) with high speed, high precision, and the CPLD ( EPM7128STC100) with powerful logical-processing capability as the control of the core to reach the complex welding process control level based on software programme.
数字化焊接电源以运算速度快、精度高、数据处理能力强的数字信号处理器（TMS320F2812）结合逻辑处理功能强大的CPLD（EPM7128STC100）为控制核心，以软件编程的方式实现了对复杂焊接过程的控制。 - Multicore processor performances with different memory sharing levels are compared which help to determine to share the memory at the L2 cache level.
比较了不同共享级别条件下多核处理器的性能，确定了在二级Cache级别进行共享。 - In order to optimize the performance the integrity tree in the embedded processor, the MGT hashes the nodes on low levels at a fine granularity; hash the nodes on upper level at a coarse granularity.
为了能提高完整树在嵌入式处理器中的性能，MGT树采用细粒度的散列方式计算完整树中的低层次节点；采用粗粒度的散列方式计算完整树中的高层次节点。 - The network processor has been widely used in data network access equipment for its hardware level processing performance by adopting flexible software system.
网络处理器能够通过灵活的软件体系提供硬件级的处理性能，已经在数据网络接入设备中被广泛使用。 - Modern digit signal processor ( DSP) achieve instruction level parallelism with superscalar or very long instruction word ( VLIW).
现代数字信号处理器（DSP）一般采取超长指令字或是超标量来实现指令级并行。 - Arbitration processor uses TMR ( Three Module Redundant) system and the chip level fault-tolerant design technology to improve reliability.
仲裁处理器使用三模冗余系统，采用芯片级的容错设计技术，具有很高的可靠性。